The present invention relates to flash memories and, more particularly, to methods of transforming data for more reliable storage in a flash memory.
Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. Now it is possible to read the stored bit by checking the threshold voltage of the cell—if the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage—all that is needed is to correctly identify in which of the two states the cell is currently located. For that purpose it suffices to make a comparison against a reference voltage value that is in the middle between the two states, and thus to determine if the cell's threshold voltage is below or above this reference value.
FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurity concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory. The terms “writing” and “programming” are used interchangeably herein.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages.
In recent years a new kind of flash device has appeared on the market, using a technique conventionally called “Multi Level Cells” or MLC for short. (This nomenclature is misleading, because the previous type of flash cells also has more than one level: they have two levels, as described above. Therefore, the two kinds of flash cells are referred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells” (MBC).) The improvement brought by the MBC flash is the storing of two bits in each cell. (In principle MBC also includes the storage of more than two bits per cell. In order to simplify the explanations, the two-bit case is emphasized herein. It should however be understood the present invention is equally applicable to flash memory devices that support more than two bits per cell.) In order for a single cell to store two bits of information the cell must be able to be in one of four different states. As the cell's “state” is represented by its threshold voltage, it is clear an MBC cell should support four different valid ranges for its threshold voltage. FIG. 1B shows the threshold voltage distribution for a typical MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one of the states. As for the SBC case, each state is actually a range of threshold voltages and not a single threshold voltage. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari.
When encoding two bits in an MBC cell as one of the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”. (In the discussion below the following notation is used—the two bits of a cell are called the “lower bit” and the “upper bit”. An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”. One must understand that the selection of this terminology and notation is arbitrary, and other names and encodings are possible). Using this notation, the left-most state represents the case of “11”. The other three states are illustrated as assigned in the following order from left to right—“10”, “00”, “01”, One can see an example of an implementation of an MBC NAND flash device using such encoding as described above in U.S. Pat. No. 6,522,580 to Chen, which patent is incorporated by reference for all purposes as if fully set forth herein. See in particular FIG. 8 of the Chen patent. It should be noted though that the present invention does not depend on this assignment of the states, and there are other ordering that can be used. When reading an MBC cells content, the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to one reference voltage, and several comparisons may be necessary. For example, in the case illustrated in FIG. 1B, one way to read the lower bit is first to compare the cell's threshold voltage to a reference comparison voltage V1 and then, depending on the outcome of the comparison, to compare the cell's threshold voltage to either a zero reference comparison voltage or a reference comparison voltage V2. Another way to read the lower bit is to compare the cell's threshold voltage unconditionally to both the zero reference voltage and V2. In either case, two comparisons are needed.
MBC devices provide a great advantage of cost—using a similarly sized cell one stores two bits rather than one. However, there are also some drawbacks to using MBC flash—the average read and write times of MBC memories are longer than of SBC memories, resulting in lower performance. Also, the reliability of MBC is lower than SBC. This can easily be understood—the differences between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.) that may have gone unnoticed in SBC because of the large gap between the two states, might cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower quality specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles. Thus there are advantages to using both MBC cells and SBC cells, and the selection can be different depending on the application's requirements.
While the above explanations deal with floating-gate flash memory cells, there are other types of flash memory technologies. For example, in the NROM flash memory technology there is no conductive floating gate but instead there is an insulating layer trapping the electric charge. The present invention is equally applicable to all flash memory types, even though the explanations herein are given in the context of floating-gate technology.
There are several sources of errors in flash memory devices. The present invention is mainly concerned with a specific source of error commonly called “Program Disturb” or “PD” for short. The PD effect causes cells, that are not intended to be written, to unintentionally move from their initial left-most state to some other state. (The explanations herein assume the common practice, also used in FIGS. 1A and 1B, of drawing the threshold voltage axis such that its left direction represents lower values. This is an arbitrary practice and should not be construed to limit the scope of the present invention in any way). Referring to the two-bit-per-cell example of FIG. 1B, cells that are in the leftmost state corresponding to bit values of “11” (or in other words, to the cell's erased state) and that are supposed to remain in such state, are found to be in the next-to-leftmost state of “10”, resulting in one bit out of the two bits stored in such cells to be incorrect. In some cases, especially in cells storing more than two bits per cell and having more than four states, PD effects might turn out not only as a move from the leftmost state to its immediately adjacent state, but also as a move from the leftmost state to more distant states, and also as a move from a state that is not the leftmost state to another state to its right (i.e. having a higher threshold voltage). However, the case described first above of moving from the leftmost state to its immediately adjacent neighboring state is the most common, and will be used herein for all examples and explanations without limiting the generality of the methods of the present invention.
By way of background for a discussion of the reason for the PD effect, FIG. 2, which is identical to FIG. 1 of the Chen patent, is a block diagram of a typical prior art flash memory device. A memory cell array 1 including a plurality of memory cells M arranged in a matrix is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5. Column control circuit 2 is connected to bit lines (BL) of memory cell array 1 for reading data stored in the memory cells (M), for determining a state of the memory cells (M) during a program operation, and for controlling voltage levels of the bit lines (BL) to promote the programming or to inhibit the programming. Row control circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply programming voltages combined with the bit line voltage levels controlled by column control circuit 2, and to apply an erase voltage coupled with a voltage of a p-type region on which the memory cells (M) are formed. C-source control circuit 4 controls a common source line connected to the memory cells (M). C-p-well control circuit 5 controls the c-p-well voltage. Typically, in a NAND flash device, the cells controlled by one word line correspond to one or two pages of the device, and the word lines are organized into blocks, with each block typically including a number of word lines that is a moderate power of 2, e.g., 25=32. A page is the smallest unit of a NAND flash device whose cells can be programmed together. A block is the smallest unit of a NAND flash device whose cells can be erased together.
The data stored in the memory cells (M) are read out by column control circuit 2 and are output to external I/O lines via an I/O line and a buffer in data input/output circuit 6. Program data to be stored in the memory cells are input to the buffer in data input/output circuit 6 via the external I/O lines, and are transferred to the column control circuit 2. The external I/O lines are connected to a controller 20.
Command data for controlling the flash memory device are input to a command interface connected to external control lines that are connected with controller 20. The command data inform the flash memory of what operation is requested. The input command is transferred to a state machine 8 that controls column control circuit 2, row control circuit 3, c-source control circuit 4, c-p-well control circuit 5 and data input/output circuit 6. State machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
Controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from memory array 1, and provides or receives such data, respectively. Controller 20 converts such commands into command signals that can be interpreted and executed by command circuits 7. Controller 20 also typically contains buffer memory for the user data being written to or read from memory array 1. A typical memory system includes one integrated circuit chip 21 that includes controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
The reason for the PD effect is easy to understand when reviewing the voltages applied to the cells of a NAND flash device when programming a page. When programming a page of cells, a relatively high voltage is applied to the word line connected to the control gates of the cells of the page. What decides whether a certain cell threshold voltage is increased as a result of this control gate voltage is the voltage applied to the bit line connected to that cell. A cell that is not to be written with data (that is—that is to remain erased, representing an all-one state), has its bit line connected to a relatively high voltage level that minimizes the voltage difference across the cell. A cell that is to be written has its bit line connected to low voltage, causing a large voltage difference across the cell, and resulting in the cell's threshold voltage getting increased, thus moving the cell to the right on the voltage axis of FIG. 1B and causing the cell's state to change.
However, even though cells that are not meant to be written have a lower voltage difference across them than cells that are meant to be written, the cells that are not to be written still have some voltage difference across them. If the page to be written has some cells that are written to high threshold voltages (for example, to the rightmost state), then the voltage difference across non-programmed cells gets higher. This is because all control gates of all cells of the page get the same voltage applied to them, and the higher the threshold voltage to be reached, the higher is that applied voltage. Therefore the need to apply higher control gate (i.e. word line) voltage to some cells results in higher voltage differences at the non-programmed cells. Even though the cells are designed with the goal of not being affected by such anticipated voltage differences, in actual NAND flash devices such voltage differences stress the cells and might result in some of the cells changing their state even though this was neither intended nor desired.
To summarize the above explanation, PD is an effect in which when programming a page of cells, some cells that are intended to remain in the leftmost erased state end up in another state, resulting in bit errors when reading those cells.
PD effects can be empirically and statistically measured, and counter-measures in the form of error correction schemes may be applied to handle them. Flash device manufacturers are aware of this source of potential errors, and they take it into account when recommending to their customers the level of error correction the customers should use. So when a manufacturer of a two-bit-per-cell MBC flash device recommends a 4-bit ECC scheme (meaning that every 512 bytes of user data should be protected against the occurrence of up to four bit errors), he may base this recommendation on a statistical analysis that assumes a random data pattern stored into the device and on the probability that a PD-type error will occur under such circumstances. Obviously, other error sources and types are also taken into account in such calculations.
Unfortunately, typical real-life user data are not random. Measurements on real-life user files show that the various possible states of the cells do not have equal probability to occur. As the leftmost state of the cells is the default value of cells not being written to, this state is the most frequent. This is easy to understand—a section of memory not initialized, or not used within a file, very often corresponds to cells in the erased state.
As a result, in real-life applications the problem of PD errors is more severe than what is expected based on random data patterns statistical calculations. Relatively many cells will be in the erased state that is the most vulnerable state to PD errors, and therefore more PD errors than are predicted by random data distribution models will actually occur.
The present invention deals with reducing the number of errors due to PD by manipulating the user data and controlling the actual sequences of voltage levels or states programmed into the flash memory. By making sure that only a limited fraction of the cells in the flash memory (or in a page of the flash memory) are programmed to the erase state, which is the state most vulnerable to the PD effect, we can minimize the amount of error due to PD.
Even though the present invention is mainly concerned with reducing PD errors, it is also applicable for reducing the effect of other undesirable phenomena in the flash memory. For example, another error source in the flash memory is leakage of the stored charge from a cell's floating gate, causing a threshold voltage drift. Similarly to PD errors, this error source is also influenced by the user data programmed into the flash memory over time. The reason for this is that the amount of charge leakage depends on the quality of the insulation layer between the floating gate and the conductive channel of the cell's transistor. However the quality of the insulation layer changes with time. The more charge transferred through the insulation layer by applying high stress in the form of high voltage levels differences across the insulation layer, the weaker the insulation layer becomes. As a result, a cell that has sustained many programming and erase (P/E) cycles exhibits a higher error rate than a cell that has sustained few P/E cycles. Moreover, if we compare two cells that have sustained the same number of P/E cycles, but on the average one of the cells has been programmed to higher voltage levels than the other cell, then the cell that has been programmed to higher voltage levels is expected to exhibit a higher error rate than the other cell due to the higher stress applied to the insulation layer of the cell that has been programmed to higher voltage levels. This means that the error rates of a flash device due to P/E cycles also depend on the user data that have been programmed to the flash device. If the user data are statistically distributed in such a way that higher voltage levels are frequently programmed, then the flash memory device will suffer from higher error rates and become less reliable.
Therefore, it is desirable to provide a flash memory device that is more reliable than prior art flash memory devices in the sense of being less vulnerable to phenomena such as PD, especially when used in real-life scenarios where user data are not random and the actual voltage levels programmed into the flash memory are not uniformly distributed over all possible voltage levels.